Section 5

PROBLEMS

SECTIONS 2-1 AND 2-2

2-1 Convert these binary numbers to decimal.

1. 10110
2. 10001101
3. 100100001001
4. 1111010111
5. 10111111

2-2 Convert the following decimal values to binary.

1. 37
2. 14
3. 189
4. 205
5. 2313
6. 511

2-3 what is the  largest decimal value that can be represented by an 8-bit binary number? A 16-bit number?

SECTION 2-3

2-4 Convert each octal number to its decimal equivalent.

1. 743
2. 36
3. 3777
4. 257
5. 1204

2-5 Convert each of the following decimal numbers to octal.

1. 59
2. 372
3. 919
4. 65,536
5. 255

2-6 Convert each of the octal values from Problem 2-4 to binary.

2-7 Convert the binary numbers in Problem 2-1 to octal.

2-8 List the binary numbers in Problem 2-1 to octal.

2-9 When a large decimal number is to be converted to binary, it is sometimes easier to convert it first to octal, and then from octal to binary. Try this procedure for 2313 and compare it with the procedure used in problem 2-2(e).

SECTION 2-4

2-10 Convert these hex values to decimal.

1. 92
2. 1A6
3. 37FD
4. 2CO
5. 7FF

2-11 Convert these decimal values to hex.

1. 75
2. 314
3. 2048
4. 25,619
5. 4095

2-12 Convert the binary numbers in Problem 2-1 to hexadecimal.

2-13 Convert the  hex values in problem 2-10 to binary.

2-14 In most microcomputers the addresses of memory locations are specified in hexadecimal. These addresses are sequential numbers that identify each memory circuit.

1. A particular microcomputer store an 8-bit number in each memory location. If the memory addresses range from 0000 to FFFF, how many memory locations are there?
2. Another microcomputer is specified to have 4096 memory locations. What range of hex addresses does this computer use?

2-15 List the hex numbers in sequence from 280 to 2A0.

SECTION 2-5

2-16 Encode these decimal numbers in BCD

1. 47
2. 962
3. 187
4. 42,689,627
5. 1204

How many bits are required to represent the decimal numbers in the range from 0 to 999 using straight binary code? Using BCD code?

2-18 The following numbers are in BCD. Convert them to decimal.

1. 1001011101010010
2. 000110000100
3. 0111011101110101
4. 010010010010

SECTION 2-8

2-19 Represent the statement “X=25/Y” in ASCII code (excluding quotes). Attach an even-parity bit.

2-20 Attach an even-parity bit to each of the ASCII codes for problem 2-19 and give the results in hex.

2-21 The following code groups are being transmitted. Attach an even-parity bit to each group.

1. 10110110
2. 00101000
3. 11110111

SECTION 2-9

2-22 Convert the following decimal numbers to BCD code and then attach an odd-parity bit.

1. 74
2. 38
3. 165
4. 9201

2-23. In a certain digital system, the decimal numbers from 000 through 999 are represented in BCD code. An odd-parity bit is also included at the of each code group. Examine each of the code groups below and assume that each one has just been transferred from one location to another. some of the groups contain errors. Assume taht no more than two errors have occured for each group. Determine which of the code groups have a single error and which of them definitely have a double error. (Hint: Remember that this is a BCD code.)

1. 1001010110000
2. 0100011101100
3. 0111110000011
4. 1000011000101

2-24 Suppose that the  receiver received the following data from the transmitter of Example 2-10.

0 1 0 0 1 0 0 0

1 1 0 0 0 1 0 1

1 1 0 0 1 1 0 0

1 1 0 0 1 0 0 0

1 1 0 0 1 1 0 0

What errors can be the  receiver determine in these received data?

DRILL QUESTIONS

2-25 Perform each of the following conversions. For some of them, you may want to try several methods to see which one works best  for you. For example, a binary-to-decimal conversion may be  done  directly, or it may be done as a binary-to-octal conversion followed by an octal-to-decimal conversion.

DRILL QUESTIONS

2-25. Perform each of the following coversions. For some of them, you may want to try several methods to see which one works best for you. For example, a binary-to-decimal conversion may be done directly, or it may be done as a binary-to-octal conversion followed by an octal-to-decimal conversion.

1. 1417=____________
2. 255 =____________
3. 11010001=________
4. 11101010000100111=______________
5. 111010110000100111=_____________
6. 2497=____________
7. 511=_____________
8. 235=_____________
9. 4316=____________
10. 7A9=_____________
11. 3E1c=____________
12. 1600=____________
13. 38,187=___________
14. 865=_____________(BCD)
15. 10010100011 (BCD)=__________
16. 465=_____________
17. B34=_____________
18. 01110100(BCD)=_____________
19. 111010=__________(BCD)

2-26. Represent the  decimal value 37 in each of the following ways.

1. straight binary
2. BCD
3. Hex
4. ASCII
5. Octal

2-27 Fill in the blanks with the correct word or words.

1. Conversion from decimal to _______requires repeated division by 8.
2. Conversion from decimal to hex requires repeated division by_______.
3. In the BCD code, each___________ is  converted to its 4-bit binary equivalent.
4. The_________code has the characteristic that only one bit changes in going from one step to the next.
5. A transmitter attaches a________to a code group to allow the receiver to detect_______.
6. The__________code is the most common alphanumeric code used in computer systems.
7. __________and_________are often used as a convenient way to represent large binary numbers.

2-28. Write to binary number that results when each of the following numbers is incremented by one: (a) 0111 (b) 010000 (c) 1110

2-29. Repeat Problem 2-28 for the decrement operation.

2-30. Write the number that results when each of the following is incremented:

1. 7777
2. 7777
3. 2000
4. 2000
5. 9FF
6. 1000

2-31. Repeat problem 2-30 for the decrement operation.

CHALLENGING EXERCISES

2-32. Perform the following conversions between base-5 and decimal

1. 3421=___________
2. 726 =___________

2-33 Convert the following binary number directly into its base-4 equivalent: 01001110

2-34 Construct a table showing the binary, octal, hex and BCD representations of all decimal numbers from 0 to 15. Compare your table with Table 2-3.

Implications of DeMorgan’s Theorems

Let us examine these teorems (16) and (17) from the standpoint of logic circuits. First, consider theorem (16), X + y =x.y The left-hand side of the equation can be viewed as the output of a NOR gate whose inputs are x and y. The right-hand side of the equation, on the other hand, is the result of first inverting both x and y and then putting them through an AND gate. These two representations are equivalent and illustrated in Figure 3-26(a). Figure 3-26 (a) Equivalent circuits implied by theorem (16); (b)alternative symbol for the NOR function. Figure 3-27 (a) Equivalent circuits implied by theorem (17); (b) alternative symbol for the NAND function. What this means is that an AND gate with INVERTERs on each of its inputs is equivalent to a NOR gate. In fact, both representations are used to represent the NOR function. When the AND gate with inverted inputs is used to represent the NOR function, it is usually drawn as shown in Figure 3-26(b), where the small circles on the inputs represent the inversion operation. Now consider theorem (17), X.Y=X+Y The left side of the equation can be implemented by a NAND gate with inputs x and y. The right side can be implemented by first inverting inputs x and y and then putting them through an OR gate. These two equivalent representations are shown in Figure 3-27(a). The OR gate with INVERTERs on each of its inputs is equivalent to the NAND gate. In fact, both representations are used to represent the NAND function. When the OR gate with inverted inputs is used to represent the NAND function, it is usually drawn as shown in Figure 3-27(b), where the circles again represent inversion.

WHICH GATE REPRESENTATION TO USE

Some logic-circuit designers and many textbooks use only the standard logic-gate symbols in their circuit schematics. While this practice is not incorrect, it does nothing to make the circuit operation easier to follow. Proper use of the alternate gate symbols in the circuit diagram can make the circuit operation easier to follow. Proper use of the alternate gate symbols in the circuit diagram can make the circuit operation much clearer. This can be illustrated by considering the example shown in Figure 3-36.

The circuit in the Figure 3-36(a) contains three NAND gates connected to produce an output Z that depends on inputs A, B, C, D. The circuit diagram uses the standard symbol for  each of the NAND gates. While this diagram is logically correct, it does not facilitate any understanding of how the circuit functions. The improved circuit representations given in Figure 3-36(b) and (c), however, can be analyzed more easily to determine the circuit operation.

The representation of Figure 3-36(b) is obtained from from the original circuit diagram by replacing NAND gate 3 with its alternate symbol. In this diagram, output Z is taken from a Nand gate symbol that has an active-HIGH output. Thus, we can say that Z will go HIGH when either X or Y is LOW. Now, since X and Y each appear at the output of NAND symbols having active-LOW outputs, we can say that Z will go LOW only if A=B=1, and Y will go LOW only if C=D=1. Putting this all together, we can describe the circuit operation as follows:

Output Z will go HIGH whenever either A=B=1 or C=D=1 (or both).

This description can be translated to truth-table form by setting Z=1 for those cases where A=B=1, and for those cases where C=D=1. For all other cases, Z is made a 0. The resultant truth table is shown in Figure 3-36(d).

The representation of Figure 3-36(c) is obtained from the original circuit diagram by replacing NAND gates 1 and 2 by their alternate symbols. In this equivalent representation the Z ouput is taken from a NAND gate that has an active-LOW output. Thus, we can say that Z will go LOW only when X=Y=1. Since X and Y are active-HIGH outputs, we can say that X will be HIGH when either A or B is LOW, and Y will be HIGH when either C or D is LOW. Putting this all together, we can describe the circuit operation as follows:

Output Z will  go LOW only when A or  B is LOW and C or D is LOW.

This description can be translated to truth-table by making Z=0 for all cases where at least one of the A or B inputs is LOW at the same time that at least one of the C or D inputs is LOW. For all other cases, Z is made a 1. The resultant truth table is the same as that obtained for the circuit diagram for the circuit diagram of Figure 3-36(b).