Digital Systems

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WHICH GATE REPRESENTATION TO USE

Some logic-circuit designers and many textbooks use only the standard logic-gate symbols in their circuit schematics. While this practice is not incorrect, it does nothing to make the circuit operation easier to follow. Proper use of the alternate gate symbols in the circuit diagram can make the circuit operation easier to follow. Proper use of the alternate gate symbols in the circuit diagram can make the circuit operation much clearer. This can be illustrated by considering the example shown in Figure 3-36.

The circuit in the Figure 3-36(a) contains three NAND gates connected to produce an output Z that depends on inputs A, B, C, D. The circuit diagram uses the standard symbol for  each of the NAND gates. While this diagram is logically correct, it does not facilitate any understanding of how the circuit functions. The improved circuit representations given in Figure 3-36(b) and (c), however, can be analyzed more easily to determine the circuit operation.

The representation of Figure 3-36(b) is obtained from from the original circuit diagram by replacing NAND gate 3 with its alternate symbol. In this diagram, output Z is taken from a Nand gate symbol that has an active-HIGH output. Thus, we can say that Z will go HIGH when either X or Y is LOW. Now, since X and Y each appear at the output of NAND symbols having active-LOW outputs, we can say that Z will go LOW only if A=B=1, and Y will go LOW only if C=D=1. Putting this all together, we can describe the circuit operation as follows:

Output Z will go HIGH whenever either A=B=1 or C=D=1 (or both).

This description can be translated to truth-table form by setting Z=1 for those cases where A=B=1, and for those cases where C=D=1. For all other cases, Z is made a 0. The resultant truth table is shown in Figure 3-36(d).

The representation of Figure 3-36(c) is obtained from the original circuit diagram by replacing NAND gates 1 and 2 by their alternate symbols. In this equivalent representation the Z ouput is taken from a NAND gate that has an active-LOW output. Thus, we can say that Z will go LOW only when X=Y=1. Since X and Y are active-HIGH outputs, we can say that X will be HIGH when either A or B is LOW, and Y will be HIGH when either C or D is LOW. Putting this all together, we can describe the circuit operation as follows:

Output Z will  go LOW only when A or  B is LOW and C or D is LOW.

This description can be translated to truth-table by making Z=0 for all cases where at least one of the A or B inputs is LOW at the same time that at least one of the C or D inputs is LOW. For all other cases, Z is made a 1. The resultant truth table is the same as that obtained for the circuit diagram for the circuit diagram of Figure 3-36(b).

November 9, 2007 - Posted by | Digital Systems

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